The present invention relates to periodic signal generators, and more particularly to a direct digital synthesizer (DDS) having a linear feedback shift register configured as a counter to determine when to make frequency/phase changes.
A direct digital synthesizer basically consists of an accumulator that acts as an address generator for a memory. The memory contains a digital representation of a cycle of a desired waveform, such as a sine function. An increment register provides an increment by which the address from the accumulator is changed for each cycle of a reference clock. The larger the increment, the greater the frequency as it requires fewer clock cycles to cycle through the memory, i.e., through one cycle of the desired waveform. The increment may be either an integer or a fraction or combination thereof, with only the integer portion of the resulting accumulation being used as the address for the memory.
For certain types of testing the frequency and/or the phase of the waveform from the DDS needs to be changed. To change the frequency a new value is loaded into the index register so that for each clock cycle the new value is added in the accumulator to produce the addresses for the memory. To change the phase a jump value needs to be added to the accumulator for only one clock cycle without changing the value in the index register. Therefore a switch is provided between the accumulator and the index and jump registers to switch the jump register to the accumulator input for one clock cycle and otherwise switch the index register to the accumulator input.
For very high frequency applications, where the internal DDS clock is at one gigahertz or greater, the external circuitry that runs with the DDS cannot keep up in speed with the internal circuitry. Such external circuitry may run in the 20-50 MHz range, which is considerably slower than the one gigahertz internal clock speed. This speed disparity can result in the missing of reference clock pulses during switching of frequency and particularly phase. The missing clock pulses result in erroneous phase response in the output waveform, i.e., where a 180 degree phase shift at a zero crossing is desired, the phase shift may occur at another instant in time, resulting in distortion of the desired output waveform.
Therefore what is desired is a direct digital synthesizer that can switch at the internal clock speeds so that no clock pulses are missed when changing frequency or phase of the desired waveform.